The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
딥 서브미크론 기술에서는 프로세스 변화가 VLSI 칩의 성능과 수율에 큰 영향을 미칠 수 있습니다. 이러한 변화에 대한 대책으로 포스트실리콘 튜닝이 제안되었다. 클럭 트리에 삽입된 프로그래밍 가능 지연 요소(PDE)를 통해 플립플롭(FF)의 클럭 타이밍을 조정하는 지연 시간 보정이 이 방법으로 분류됩니다. 우리는 소량의 FF의 클럭 타이밍을 측정하고 통계적 모델을 기반으로 나머지 FF의 클럭 타이밍을 추정하여 요소의 지연 값을 결정하는 새로운 왜곡 보정 방법을 제안합니다. 또한, 우리가 제안하는 방법은 재작성 제약 조건이 전체 단모듈성 조건을 만족하므로 이산 PDE 지연 값을 결정할 수 있다.
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부
Yuko HASHIZUME, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, "Post-Silicon Clock-Timing Tuning Based on Statistical Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 9, pp. 2322-2327, September 2008, doi: 10.1093/ietfec/e91-a.9.2322.
Abstract: In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.9.2322/_p
부
@ARTICLE{e91-a_9_2322,
author={Yuko HASHIZUME, Yasuhiro TAKASHIMA, Yuichi NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Post-Silicon Clock-Timing Tuning Based on Statistical Estimation},
year={2008},
volume={E91-A},
number={9},
pages={2322-2327},
abstract={In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.},
keywords={},
doi={10.1093/ietfec/e91-a.9.2322},
ISSN={1745-1337},
month={September},}
부
TY - JOUR
TI - Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2322
EP - 2327
AU - Yuko HASHIZUME
AU - Yasuhiro TAKASHIMA
AU - Yuichi NAKAMURA
PY - 2008
DO - 10.1093/ietfec/e91-a.9.2322
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2008
AB - In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.
ER -