The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
디지털 데이터 전송 수신기에 사용되는 대부분의 디지털 위상 고정 루프(DPLL)는 초기에 입력 주파수와 위상을 빠르게 획득해야 하고 정상 상태에서는 상당한 지터 감소가 필요하므로 그에 따라 DPLL 루프 대역폭을 조정하는 것이 좋습니다. 본 논문에서는 각기 다른 잡음 환경과 하드웨어 요구 사항에 대해 빠른 획득과 상당한 지터 감소를 가능하게 하는 대역폭 조정(적응형) 알고리즘이 제시됩니다. RLS(Recursive Least Square) 기준을 기반으로 하는 이 알고리즘은 주어진 시간 순간에 지터 변동을 최소화하려고 시도하여 가장 빠른 초기 획득 시간을 달성하는 이중 루프 DPLL에 대한 제어 매개변수의 최적 시퀀스를 제안합니다. 이 알고리즘은 짧은 초기 프리앰블 기간이 필요한 이동 통신, 근거리 통신망 및 디스크 드라이버에서 반송파 복구 또는 클럭 복구에 사용될 수 있습니다.
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부
Tae Hun KIM, Beomsup KIM, "Dual-Loop Digital PLL Design for Adaptive Clock Recovery" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2509-2514, December 1998, doi: .
Abstract: Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2509/_p
부
@ARTICLE{e81-a_12_2509,
author={Tae Hun KIM, Beomsup KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Dual-Loop Digital PLL Design for Adaptive Clock Recovery},
year={1998},
volume={E81-A},
number={12},
pages={2509-2514},
abstract={Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Dual-Loop Digital PLL Design for Adaptive Clock Recovery
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2509
EP - 2514
AU - Tae Hun KIM
AU - Beomsup KIM
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.
ER -