The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 민감하지만 최대 클록 주파수 결정에 영향을 미치지 않는 새로운 종류의 잘못된 경로를 소개합니다. 이러한 잘못된 경로는 대기 상태에 의해 제어되는 다중 클럭 작업에 존재하며 이러한 경로의 지연 시간은 클럭 주기보다 클 수 있습니다. 본 논문에서는 기호 상태 탐색을 기반으로 이러한 대기 중인 잘못된 경로를 탐지하는 방법을 제안합니다. 이 방법에서는 각 레지스터의 업데이트 주기를 이용하여 각 경로의 최대 허용 클럭 주기를 계산합니다.
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부
Kazuhiro NAKAMURA, Shinji KIMURA, Kazuyoshi TAKAGI, Katsumasa WATANABE, "Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2515-2520, December 1998, doi: .
Abstract: This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2515/_p
부
@ARTICLE{e81-a_12_2515,
author={Kazuhiro NAKAMURA, Shinji KIMURA, Kazuyoshi TAKAGI, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis},
year={1998},
volume={E81-A},
number={12},
pages={2515-2520},
abstract={This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2515
EP - 2520
AU - Kazuhiro NAKAMURA
AU - Shinji KIMURA
AU - Kazuyoshi TAKAGI
AU - Katsumasa WATANABE
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
ER -