The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
많은 임베디드 시스템에서는 오프칩 커패시턴스가 온칩 커패시턴스보다 훨씬 크기 때문에 오프칩 구동에 상당한 양의 전력이 소비됩니다. 본 논문에서는 오프칩 구동에 소요되는 전력을 줄이기 위한 명령어 스케줄링 기법을 제안한다. 이 기술은 명령어 캐시 누락이 발생할 때 온칩 캐시와 주 메모리 사이의 데이터 버스 스위칭 활동을 최소화합니다. 스케줄링 문제가 공식화되고 두 가지 스케줄링 알고리즘이 제시됩니다. 실험 결과는 제안된 알고리즘의 효과성과 효율성을 입증합니다.
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Hiroyuki TOMIYAMA, Tohru ISHIHARA, Akihiko INOUE, Hiroto YASUURA, "Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2621-2629, December 1998, doi: .
Abstract: In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2621/_p
부
@ARTICLE{e81-a_12_2621,
author={Hiroyuki TOMIYAMA, Tohru ISHIHARA, Akihiko INOUE, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches},
year={1998},
volume={E81-A},
number={12},
pages={2621-2629},
abstract={In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2621
EP - 2629
AU - Hiroyuki TOMIYAMA
AU - Tohru ISHIHARA
AU - Akihiko INOUE
AU - Hiroto YASUURA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
ER -