The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 작업 태스크의 컨텍스트를 저장하는 레지스터 뱅크를 이용하여 컨텍스트 전환 시간을 줄이는 방법을 제안한다. 하드웨어 비용과 성능은 VHDL의 레지스터 뱅크와 컨트롤러를 모델링하여 측정되었습니다. (1) SRAM 모듈로 구현되는 레지스터 뱅크에 비해 훨씬 적은 하드웨어 비용으로 컨트롤러를 구현할 수 있다. (2) 소프트웨어 구현에 비해 컨텍스트 스위칭 시간을 50% 이하로 줄일 수 있다. (3) 제안된 아키텍처와 이전 작업(HW에 구현된 RTOS)을 결합하면 하드 실시간 시스템의 훨씬 더 높은 성능을 얻을 수 있습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Jun-ichi ITO, Takumi NAKANO, Yoshinori TAKEUCHI, Masaharu IMAI, "Effectiveness of a High Speed Context Switching Method Using Register Bank" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2661-2667, December 1998, doi: .
Abstract: This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2661/_p
부
@ARTICLE{e81-a_12_2661,
author={Jun-ichi ITO, Takumi NAKANO, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Effectiveness of a High Speed Context Switching Method Using Register Bank},
year={1998},
volume={E81-A},
number={12},
pages={2661-2667},
abstract={This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Effectiveness of a High Speed Context Switching Method Using Register Bank
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2661
EP - 2667
AU - Jun-ichi ITO
AU - Takumi NAKANO
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.
ER -