The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 클럭 주파수를 고려한 ASIP 성능 최적화 방법을 제안한다. 명령어 집합 프로세서의 성능은 응용 프로그램의 실행 시간을 이용하여 측정할 수 있으며, 이는 응용 프로그램을 수행하는 클럭 주기를 인가된 클럭 주파수로 나눈 값으로 결정될 수 있다. 따라서 주어진 설계 제약 조건 하에서 프로세서의 성능을 최대화하려면 클록 주파수도 조정되어야 합니다. 실험 결과는 제안된 방법이 클럭 주파수를 고려하여 최적의 FU 조합을 결정하는 것을 보여주었다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Katsuya SHINOHARA, Norimasa OHTSUKI, Yoshinori TAKEUCHI, Masaharu IMAI, "A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2356-2365, November 1999, doi: .
Abstract: This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2356/_p
부
@ARTICLE{e82-a_11_2356,
author={Katsuya SHINOHARA, Norimasa OHTSUKI, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency},
year={1999},
volume={E82-A},
number={11},
pages={2356-2365},
abstract={This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2356
EP - 2365
AU - Katsuya SHINOHARA
AU - Norimasa OHTSUKI
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
ER -