The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
VLSI 설계에서 트랜지스터 수가 증가함에 따라 점점 더 많은 설계 그룹이 설계를 결합하는 효율적인 방법을 찾으려고 노력하고 있습니다. 인터넷은 분산 컴퓨팅과 리소스 공유를 특징으로 합니다. 결과적으로 계층적 설계는 인터넷 환경에서 적절하게 해결될 수 있다. 본 논문에서는 면적 최소화 평면도 문제를 해결하여 인터넷 환경의 용이성을 입증합니다. 우리는 인터넷을 활용한 RMG 알고리즘을 제안한다. 전송 지연 모델을 기반으로 RMG 알고리즘은 평면도 트리의 주요 경로를 단축하여 컴퓨팅 시간을 줄입니다. 우리의 실험 결과는 인터넷이 전자 설계 자동화(EDA)에 적합하다는 것을 보여줍니다.
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부
Jiann-Horng LIN, Jing-Yang JOU, Iris Hui-Ru JIANG, "Internet-Based Hierarchical Floorplan Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2414-2423, November 1999, doi: .
Abstract: With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2414/_p
부
@ARTICLE{e82-a_11_2414,
author={Jiann-Horng LIN, Jing-Yang JOU, Iris Hui-Ru JIANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Internet-Based Hierarchical Floorplan Design},
year={1999},
volume={E82-A},
number={11},
pages={2414-2423},
abstract={With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Internet-Based Hierarchical Floorplan Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2414
EP - 2423
AU - Jiann-Horng LIN
AU - Jing-Yang JOU
AU - Iris Hui-Ru JIANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).
ER -