The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
캐시 메모리는 소프트웨어 성능에 영향을 미치는 주요 요소 중 하나이며, 임베디드 시스템에서도 그 사용이 점점 보편화되고 있습니다. 매개변수 변화(캐시 크기, 연관성 정도, 대체 정책, 라인 크기 등)의 효과에 대한 효율적인 분석은 동시에 임베디드 시스템 설계의 필수이자 시간 소모적인 측면입니다. 작업 및 실시간 측면을 고려해야 합니다. 우리는 캐시와 멀티태스킹 반응형 소프트웨어의 대략적인 모델에 초점을 맞춘 새로운 시뮬레이션 기반 방법론을 제안합니다. 이를 통해 정확도와 시뮬레이션 속도 사이를 원활하게 교환할 수 있습니다. 특히, 우리는 작업 내 충돌을 정확하게 고려하되 제한된 수의 이전 작업 실행만을 고려하여 작업 간 충돌을 대략적으로 고려하는 것을 제안합니다. 이 선택에 대한 근거는 임베디드 시스템의 일반적인 패턴에서 찾을 수 있습니다. 여기서 "정상적인" 데이터 흐름은 정기적인 작업 내 공통 흐름을 초래하고 긴급한 이벤트로 인해 때때로 중단되며 비관적으로는 방해가 되는 것으로 간주될 수 있습니다. 캐시 동작. 오랜 시간이 지난 후 작업을 다시 실행하면 항상 캐시에 없는 것으로 간주되고 시뮬레이션 속도가 상당히 향상되므로 이 접근 방식은 보수적입니다.
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Marcello LAJOLO, Luciano LAVAGNO, Alberto SANGIOVANNI-VINCENTELLI, "Fast Instruction Cache Simulation for Hardware/Software Co-Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2475-2484, November 1999, doi: .
Abstract: Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2475/_p
부
@ARTICLE{e82-a_11_2475,
author={Marcello LAJOLO, Luciano LAVAGNO, Alberto SANGIOVANNI-VINCENTELLI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast Instruction Cache Simulation for Hardware/Software Co-Design},
year={1999},
volume={E82-A},
number={11},
pages={2475-2484},
abstract={Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Fast Instruction Cache Simulation for Hardware/Software Co-Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2475
EP - 2484
AU - Marcello LAJOLO
AU - Luciano LAVAGNO
AU - Alberto SANGIOVANNI-VINCENTELLI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.
ER -