The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 대규모 디지털 MOS 회로를 위한 고속 타이밍 시뮬레이터인 RSPICE를 소개합니다. 새로운 테이블 기반 영역별 선형 MOS 트랜지스터 모델과 일반 하위 회로 프리미티브의 분석 솔루션을 적용하여 디지털 MOS 회로의 과도 응답을 계산합니다. 패스 트랜지스터의 본체 효과는 MOS 모델에 포함되어 있으며 플로팅 커패시터 네트워크도 이 하위 회로 프리미티브로 처리할 수 있습니다. RSPICE에서는 DC 경로가 있는 MOS 트랜지스터가 DC 연결 블록(DCCB)으로 그룹화되고 피드백 경로가 있는 DCCB가 SCC(강하게 연결된 구성 요소)로 결합됩니다. RSPICE는 Tarjan의 알고리즘에 따라 SCC를 정렬하고 정렬된 SCC를 하나씩 시뮬레이션합니다. DCCB는 RSPICE의 기본 셀이며 모든 DCCB는 하나 이상의 하위 회로 프리미티브에 매핑될 수 있습니다. 이러한 프리미티브의 과도 응답을 분석적으로 계산하기 위해 RSPICE는 조각별 선형 함수로 프리미티브의 입력 신호를 근사화합니다. 시뮬레이션 정확도와 실행 시간을 절충하기 위해 동적 창 기법과 결합된 부분 파형 및 부분 시간 수렴(PWPTC)을 적용하여 SCC를 시뮬레이션합니다. 회로 분할, 패스 트랜지스터 및 플로팅 커패시터 처리, 시뮬레이션 흐름 제어 및 파형 수정과 같은 RSPICE의 다른 주요 문제도 자세히 논의됩니다. HSPICE와 비교하면 RSPICE의 시뮬레이션 결과는 오류가 3% 미만으로 매우 정확하지만 속도는 HSPICE에 비해 1~2차수 정도 빠릅니다.
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부
Xia CAI, Huazhong YANG, Yaowei JIA, Hui WANG, "RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2492-2498, November 1999, doi: .
Abstract: RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2492/_p
부
@ARTICLE{e82-a_11_2492,
author={Xia CAI, Huazhong YANG, Yaowei JIA, Hui WANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI},
year={1999},
volume={E82-A},
number={11},
pages={2492-2498},
abstract={RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2492
EP - 2498
AU - Xia CAI
AU - Huazhong YANG
AU - Yaowei JIA
AU - Hui WANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.
ER -