The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 수정된 TSPC(True Single-Phase Clock) 포지티브 에지 트리거 D 플립플롭을 사용하여 설계된 고속 및 저전력 위상 주파수 검출기(PFD)를 소개합니다. 제안된 PFD는 19개의 트랜지스터만을 사용하여 간단한 구조를 갖는다. 이 PFD의 작동 범위는 추가 프리스케일러 회로를 사용하지 않고도 1.4GHz 이상입니다. 또한 PFD는 위상 특성이 0.01ns 미만의 불감대(Dead Zone)를 가지며 위상 감도 오차도 낮습니다. 위상 및 주파수 오류 검출 범위는 pt형 및 nc형 PFD의 경우처럼 제한되지 않습니다. 또한 PFD는 입력 신호의 듀티 사이클과 무관합니다. 또한 전하 증폭기를 기반으로 하는 새로운 전하 펌프 회로가 제시됩니다. 제안된 차지 펌프 회로의 대기 전류는 차지 펌프의 속도를 향상시키고 차지 펌프 PLL의 위상 잡음을 유발하는 전하 공유를 제거한다. 또한, 출력단을 업 및 다운 신호로부터 분리함으로써 클록 피드스루의 효과가 감소됩니다. 제안된 PFD 및 차지 펌프 회로를 사용하여 프로세스의 잠금을 검증하기 위해 0.8차 PLL을 기반으로 한 시뮬레이션 결과가 제공됩니다. 제안된 PFD 및 차지 펌프 회로는 5V 공급 전압을 갖춘 XNUMXμm CMOS 기술을 사용하여 설계되었습니다.
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부
Won-Hyo LEE, Sung-Dae LEE, Jun-Dong CHO, "A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2514-2520, November 1999, doi: .
Abstract: In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2514/_p
부
@ARTICLE{e82-a_11_2514,
author={Won-Hyo LEE, Sung-Dae LEE, Jun-Dong CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops},
year={1999},
volume={E82-A},
number={11},
pages={2514-2520},
abstract={In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage. },
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2514
EP - 2520
AU - Won-Hyo LEE
AU - Sung-Dae LEE
AU - Jun-Dong CHO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.
ER -