The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 작업 스케줄링 및 데이터 경로 할당을 위한 고급 테스트 합성 알고리즘을 제시합니다. 데이터 경로 할당은 레지스터 전송 수준의 테스트 가능성 분석을 기반으로 하는 제어 가능성 및 관찰 가능성 균형 할당 기술을 통해 달성됩니다. 반면에 스케줄링은 테스트 가능성을 향상시키기 위해 기본 스케줄링을 변경하는 변환을 다시 예약하여 수행됩니다. 스케줄링 및 할당 작업이 독립적으로 수행되는 다른 작업과 달리, 우리의 접근 방식은 스케줄링 및 할당 작업을 동시에 수행하여 통합하여 스케줄링 및 할당이 테스트 가능성에 미치는 영향을 보다 효과적으로 활용합니다. 또한 순차 루프는 설계를 테스트하기 어렵게 만드는 것으로 널리 알려져 있으므로 통합 테스트 합성 프로세스 중에 루프 생성을 방지하기 위해 레지스터 전송 수준에서 완전한(기능적 및 토폴로지) 루프 분석이 수행됩니다. 다양한 합성 벤치마크를 통해 실험 결과는 제안된 알고리즘의 장점을 명확하게 보여줍니다.
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부
Tianruo YANG, "The Integrated Scheduling and Allocation of High-Level Test Synthesis" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 1, pp. 145-158, January 1999, doi: .
Abstract: This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_1_145/_p
부
@ARTICLE{e82-a_1_145,
author={Tianruo YANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The Integrated Scheduling and Allocation of High-Level Test Synthesis},
year={1999},
volume={E82-A},
number={1},
pages={145-158},
abstract={This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.},
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - The Integrated Scheduling and Allocation of High-Level Test Synthesis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 145
EP - 158
AU - Tianruo YANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 1999
AB - This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.
ER -