The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 병렬 전달 평가 알고리즘과 뉴런 간 연결의 희소성을 잘 활용하여 순차 볼츠만 머신 프로세서에 파이프라인 구조를 성공적으로 도입했습니다. 새로운 구조는 12개의 뉴런 미만에서 하드웨어 리소스가 10,000%만 증가하여 이전 구조보다 속도가 1.2배 빠릅니다. XNUMX µm CMOS 공정 표준 셀을 사용하여 설계하고 상태 변화 확률을 분석하여 성능을 확인합니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Hongbing ZHU, Mamoru SASAKI, Takahiro INOUE, "A Pipeline Structure for the Sequential Boltzmann Machine" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 920-926, June 1999, doi: .
Abstract: In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_920/_p
부
@ARTICLE{e82-a_6_920,
author={Hongbing ZHU, Mamoru SASAKI, Takahiro INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Pipeline Structure for the Sequential Boltzmann Machine},
year={1999},
volume={E82-A},
number={6},
pages={920-926},
abstract={In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - A Pipeline Structure for the Sequential Boltzmann Machine
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 920
EP - 926
AU - Hongbing ZHU
AU - Mamoru SASAKI
AU - Takahiro INOUE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.
ER -