The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 연구에서는 유한 버퍼 크기와 동기 동작 모드를 갖춘 큐잉 모델을 사용하여 슈퍼스칼라 프로세서의 명령 실행 속도를 예측하는 새로운 분석 모델을 제시합니다. 제안된 모델은 캐시와 파이프라인 간의 성능 관계도 분석할 수 있습니다. 제안된 모델은 명령어 수준 병렬성, 분기 확률, 분기 예측의 정확성, 캐시 미스 등과 같은 다양한 종류의 아키텍처 매개변수를 고려합니다. 모델의 정확성을 입증하기 위해 광범위한 시뮬레이션을 수행하고 결과를 다음과 비교했습니다. 분석 모델. 시뮬레이션 결과, 제안한 모델은 대부분의 경우 10% 오차 내에서 정확하게 평균 실행률을 추정할 수 있는 것으로 나타났다. 제안된 모델은 시뮬레이션 방법만으로는 발견할 수 없는 성능 병목 현상의 원인을 설명할 수 있습니다. 또한 이 모델은 균형 잡힌 시스템을 설계하는 데 귀중한 정보를 제공할 수 있는 비순차적 슈퍼스칼라 프로세서의 성능에 대한 캐시 미스의 영향을 보여줄 수 있습니다.
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부
Hak-Jun KIM, Sun-Mo KIM, Sang-Bang CHOI, "System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 927-938, June 1999, doi: .
Abstract: This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_927/_p
부
@ARTICLE{e82-a_6_927,
author={Hak-Jun KIM, Sun-Mo KIM, Sang-Bang CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method},
year={1999},
volume={E82-A},
number={6},
pages={927-938},
abstract={This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 927
EP - 938
AU - Hak-Jun KIM
AU - Sun-Mo KIM
AU - Sang-Bang CHOI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.
ER -