The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
뉴로칩에서 양자화된 상호연결 신경망의 동적 거동을 조사하기 위해 1.2 µm CMOS 기술의 설계 규칙에 따라 하드웨어 신경망을 설계하고 제작했습니다. 이를 위해 우리는 세 가지 값의 상호 연결을 위해 프로그래밍 가능한 시냅스 가중치를 개발했습니다.
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부
Cheol-Young PARK, Koji NAKAJIMA, "Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 952-957, June 1999, doi: .
Abstract: In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_952/_p
부
@ARTICLE{e82-a_6_952,
author={Cheol-Young PARK, Koji NAKAJIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles},
year={1999},
volume={E82-A},
number={6},
pages={952-957},
abstract={In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 952
EP - 957
AU - Cheol-Young PARK
AU - Koji NAKAJIMA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of
ER -