The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 오버샘플링 데이터 복구 회로에 대한 분석이 제시됩니다. 입력 파형은 NRZ(Non-Return-Zero) 이진 신호로 간주됩니다. 유한 마르코프 체인 모델은 정상 상태 위상 지터 성능을 평가하는 데 사용됩니다. 이론적 분석을 통해 다양한 오버샘플링 비율에 대한 오버샘플링 데이터 복구 회로의 입력 신호 대 잡음비(SNR) 대 비트 오류율(BER)을 예측할 수 있습니다. 단일 비트당 샘플 수가 많을수록 동일한 입력 SNR에서 BER 성능이 향상됩니다. 10을 달성하려면-11 BER, 8배 오버샘플링은 2배 오버샘플링에 비해 약 16dB의 입력 신호 페널티를 갖습니다. 오버샘플링 데이터 복구 회로의 아키텍처 선택에서 복구된 클록은 입력 데이터 속도 및 입력 노이즈에 따라 각 데이터 비트 또는 여러 비트마다 업데이트될 수 있습니다. 두 가지 서로 다른 클록 업데이트 방식을 분석하고 비교했습니다. 모든 데이터 비트의 클록 업데이트 방식은 백색 잡음이 지배적인 입력 데이터에서 1.5배 오버샘플링되는 다중 비트(4비트) 클록 업데이트 방식에 비해 약 16dB의 페널티를 갖습니다. 분석 결과를 검증하기 위해 제작된 회로에 적용했습니다.
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부
Jin-Ku KANG, "Performance Analysis of Oversampling Data Recovery Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 958-964, June 1999, doi: .
Abstract: In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_958/_p
부
@ARTICLE{e82-a_6_958,
author={Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Analysis of Oversampling Data Recovery Circuit},
year={1999},
volume={E82-A},
number={6},
pages={958-964},
abstract={In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Performance Analysis of Oversampling Data Recovery Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 958
EP - 964
AU - Jin-Ku KANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.
ER -