The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 메모리 병합 로직 LSI인 FMA(Functional Memory for Addition)를 제안합니다. 이는 메모리이자 SIMD 병렬 프로세서입니다. 면적을 최소화하기 위해 PE(Precessing Element)는 여러 DRAM 워드와 비트 직렬 ALU로 구성됩니다. ALU에는 비트 단위로 추가하는 기능이 있습니다. 이 문서에서는 두 가지 FMA 실험용 LSI에 대해 설명합니다. 하나는 범용이고, 다른 하나는 영상 압축의 전체 검색 블록 매칭을 위한 것입니다. 우리는 0.18 µm 프로세스가 57,000 mm에서 50 PE를 실현한다고 추정합니다.2 205W 전력에서 1.36GOPS를 달성합니다.
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Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, "Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2400-2408, December 2000, doi: .
Abstract: We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2400/_p
부
@ARTICLE{e83-a_12_2400,
author={Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition},
year={2000},
volume={E83-A},
number={12},
pages={2400-2408},
abstract={We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2400
EP - 2408
AU - Kazutoshi KOBAYASHI
AU - Masanao YAMAOKA
AU - Yukifumi KOBAYASHI
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
ER -