The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 실을 구성하는 방법을 제시한다. 하드웨어 컴파일러 바흐. Bach는 다음과 같이 작성된 시스템 설명에서 RT 레벨 회로를 합성합니다. 바흐-C 여기서 시스템은 병렬로 실행되는 통신 프로세스로 모델링됩니다. 시스템 설명은 다음과 같이 분해됩니다. 스레드즉, 병렬로 실행되지 않는 프로세스를 그룹화하여 순차적 프로세스의 문자열입니다. 그런 다음 스레드 세트는 동작 VHDL 모델로 변환되어 동작 합성기로 전달됩니다. 제안하는 방법은 스레드 내 프로세스 간 자원 공유를 최대화하는 스레드 구성을 찾으려고 시도한다. 두 가지 실제 설계에 대한 실험에서는 회로 크기가 3.7%와 14.7% 감소한 것으로 나타났습니다. 또한 결과 게이트 레벨 회로의 크기에 대한 자세한 통계 및 분석도 보여줍니다.
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Mizuki TAKAHASHI, Nagisa ISHIURA, Akihisa YAMADA, Takashi KAMBE, "Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2456-2463, December 2000, doi: .
Abstract: This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2456/_p
부
@ARTICLE{e83-a_12_2456,
author={Mizuki TAKAHASHI, Nagisa ISHIURA, Akihisa YAMADA, Takashi KAMBE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes},
year={2000},
volume={E83-A},
number={12},
pages={2456-2463},
abstract={This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2456
EP - 2463
AU - Mizuki TAKAHASHI
AU - Nagisa ISHIURA
AU - Akihisa YAMADA
AU - Takashi KAMBE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.
ER -