The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 Salicide 공정을 위한 세포 합성 방법을 제안한다. 우리의 방법은 일부 Salicide 공정에서 사용할 수 있는 인접한 트랜지스터 간의 로컬 상호 연결을 활용하고 로컬 상호 연결의 수와 면적을 모두 고려하여 셀의 트랜지스터 배치를 최적화합니다. 이러한 방식으로 우리는 금속 와이어와 접점의 수를 줄입니다. 회로 모델은 기존의 직렬 병렬 CMOS 로직에 국한되지 않으며, 우리의 방법을 통해 CMOS 패스 트랜지스터 회로를 합성할 수 있습니다. 실험 결과는 우리의 방법이 로컬 상호 연결을 효과적으로 사용하고 셀 영역과 금속 와이어 길이를 모두 최적화한다는 것을 보여줍니다.
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Kazuhisa OKADA, Takayuki YAMANOUCHI, Takashi KAMBE, "A Cell Synthesis Method for Salicide Process Using Assignment Graph" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2577-2583, December 2000, doi: .
Abstract: In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2577/_p
부
@ARTICLE{e83-a_12_2577,
author={Kazuhisa OKADA, Takayuki YAMANOUCHI, Takashi KAMBE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Cell Synthesis Method for Salicide Process Using Assignment Graph},
year={2000},
volume={E83-A},
number={12},
pages={2577-2583},
abstract={In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - A Cell Synthesis Method for Salicide Process Using Assignment Graph
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2577
EP - 2583
AU - Kazuhisa OKADA
AU - Takayuki YAMANOUCHI
AU - Takashi KAMBE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.
ER -