The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 연구는 유한 필드에 대한 환원 불가능한 AOP(All One Polynomial)를 기반으로 하는 두 개의 새로운 비트 병렬 셀룰러 곱셈기를 제시합니다. GF(2m). AOP의 속성을 사용하여 이 연구는 컴퓨팅을 위한 효율적인 내적 곱셈 알고리즘도 제시합니다. AB2 하드웨어 구현을 위한 시간과 공간의 복잡성을 단순화할 수 있는 구조로 곱셈이 제안됩니다. 첫 번째 구조는 새로운 내적 곱셈 알고리즘을 사용하여 비트 병렬 셀룰러 아키텍처를 구성합니다. 설계된 곱셈기에는 다음의 계산 지연만 필요합니다.m+1)(T및+T무료). 두 번째로 제안된 구조는 첫 번째 구조를 수정한 것으로, 다음과 같은 요구 사항이 필요합니다.m+ 2) T무료 지연. 또한, 제안된 승수는 다음을 수행할 수 있습니다. A2iB2j 계수를 섞어서 계산합니다. i 및 j 정수. 계산 곱셈의 경우 GF(2m), 새로운 승수는 아키텍처를 단순화하고 계산을 가속화하므로 효율적인 것으로 나타났습니다. 두 가지 새로운 아키텍처는 매우 규칙적이고 단순하며 기존 셀룰러 곱셈기보다 계산 지연이 더 짧습니다.
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Chung-Hsin LIU, Nen-Fu HUANG, Chiou-Yng LEE, "Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2657-2663, December 2000, doi: .
Abstract: This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2657/_p
부
@ARTICLE{e83-a_12_2657,
author={Chung-Hsin LIU, Nen-Fu HUANG, Chiou-Yng LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture},
year={2000},
volume={E83-A},
number={12},
pages={2657-2663},
abstract={This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2657
EP - 2663
AU - Chung-Hsin LIU
AU - Nen-Fu HUANG
AU - Chiou-Yng LEE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.
ER -