The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
파이프라인 프로세서를 위한 합성 가능한 HDL 생성 방법이 제안됩니다. 제안된 방법을 사용하여 대상 프로세서의 데이터 경로 및 제어 논리 설명은 클럭 기반 명령어 세트 사양에서 생성됩니다. 실험 결과를 통해 제안한 방법의 타당성을 평가하였으며, HDL에서 기존 RT 레벨 수동 설계에 비해 프로세서 설계 시간이 획기적으로 단축되었음을 확인하였다.
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Makiko ITOH, Yoshinori TAKEUCHI, Masaharu IMAI, Akichika SHIOMI, "Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 3, pp. 394-400, March 2000, doi: .
Abstract: A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_3_394/_p
부
@ARTICLE{e83-a_3_394,
author={Makiko ITOH, Yoshinori TAKEUCHI, Masaharu IMAI, Akichika SHIOMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description},
year={2000},
volume={E83-A},
number={3},
pages={394-400},
abstract={A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.},
keywords={},
doi={},
ISSN={},
month={March},}
부
TY - JOUR
TI - Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 394
EP - 400
AU - Makiko ITOH
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
AU - Akichika SHIOMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2000
AB - A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.
ER -