The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
클럭 스큐는 고속 동기 IC의 주요 제약 사항 중 하나이므로 고성능을 얻으려면 이를 최소화해야 합니다. 그러나 클럭 스큐를 최소화하면 전체 와이어 길이가 늘어날 수 있습니다. 따라서 클록 라우팅은 주어진 스큐 바운드 내에서 수행됩니다. 지정된 스큐 바운드 아래의 클록 라우팅은 전체 와이어 길이를 줄일 수 있습니다. 본 논문에서는 링크 에지 삽입을 사용한 제한된 클록 스큐 라우팅을 위한 새로운 효율적인 알고리즘을 제안합니다. 이는 주어진 스큐 바운드를 만족하고 전체 와이어 길이가 증가하는 것을 방지합니다. 새로운 병합점 재배치 방법을 이용한 전체 와이어 길이 및 지연 시간 최소화 알고리즘뿐만 아니라 지연 차이가 큰 한 쌍의 노드에 대해 링크-에지 삽입 기법을 이용한 클럭 스큐 감소 알고리즘을 제안한다. 제안하는 알고리즘은 대부분의 기존 방법이 트리 구조의 라우팅 토폴로지를 사용하는 반면, 일반화된 그래프 모델인 새로운 클럭 라우팅 토폴로지를 구성한다. 링크 에지 추가를 위해 두 개의 노드를 선택하기 위해 새로운 비용 함수가 설계되었습니다. 이 비용 함수를 사용하면 지연 차이가 크고 거리가 작은 두 노드를 연결하여 지연 차이 또는 클럭 스큐가 줄어듭니다. 또한 라우팅 토폴로지 구성 및 와이어 크기 조정 알고리즘을 사용하여 클럭 지연을 줄입니다. 제안하는 알고리즘은 C 프로그래밍 언어로 구현된다. 실험 결과는 주어진 스큐 바운드 아래에서 전체 와이어 길이가 줄어들 수 있음을 보여줍니다.
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부
Kwang-Ki RYOO, Hyunchul SHIN, Jong-Wha CHONG, "A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1115-1122, June 2000, doi: .
Abstract: As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1115/_p
부
@ARTICLE{e83-a_6_1115,
author={Kwang-Ki RYOO, Hyunchul SHIN, Jong-Wha CHONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design},
year={2000},
volume={E83-A},
number={6},
pages={1115-1122},
abstract={As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1115
EP - 1122
AU - Kwang-Ki RYOO
AU - Hyunchul SHIN
AU - Jong-Wha CHONG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.
ER -