The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
내부 ADC의 이득 스케일링과 매우 간단한 내부 DAC를 특징으로 하는 3비트 내부 양자화기를 갖춘 0.8차 시그마-델타 변조기는 3μm 이중 폴리 이중 금속 CMOS 공정에서 설계 및 구현되었습니다. 14비트 내부 ADC의 게인 스케일링과 간단한 로직 게이트를 사용한 내부 오류 없는 DAC 설계로 변조기의 성능을 향상시켰습니다. 변조기는 시간 기반 모델링을 통해 87비트 해상도를 갖도록 각 구성 요소의 사양이 결정되며, 설계된 구성 요소는 요구 사양을 만족합니다. 87dB의 피크 SNR과 2.816dB의 동적 범위는 22kHz 베이스밴드에 대해 14MHz의 클록 속도에서 달성되었습니다. 측정 결과, 제작된 변조기는 비이상적인 입력 소스와 전압 가변 커패시터 등 모델링에서 무시된 오차 요인으로 인해 시뮬레이션보다 SNR이 XNUMXdB만큼 낮은 것으로 나타났습니다.
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부
Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, "A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1192-1198, June 2000, doi: .
Abstract: A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1192/_p
부
@ARTICLE{e83-a_6_1192,
author={Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC},
year={2000},
volume={E83-A},
number={6},
pages={1192-1198},
abstract={A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1192
EP - 1198
AU - Byung-Woog CHO
AU - Pyung CHOI
AU - Jun-Rim CHOI
AU - Dae-Hyuk KWON
AU - Byung-Ki SOHN
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.
ER -