The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 문서에서는 듀얼 차지 펌프 PLL을 기반으로 하는 새로운 병렬 클록 복구 아키텍처를 사용하여 광통신 트랜시버를 위한 3, 156 및 622Mbps 클록의 1244V 저전력 다중 속도 구현과 데이터 복구 회로(CDR)를 제시합니다. 설계된 회로는 입력 신호의 1/2 주파수인 40상 클럭 신호를 복구합니다. 일반적인 시스템에서는 입력 데이터와 복구된 클록을 비교하는 방법을 사용하는 반면, 제안 회로에서는 3/0.65비트 지연된 입력 데이터와 복구된 XNUMX상 클록 신호에 의해 생성된 직렬 데이터를 비교한다. 이 회로의 장점은 각 하위 블록이 입력 데이터 신호의 XNUMX/XNUMX 주파수를 갖기 때문에 구현이 쉽다는 것입니다. 게다가 이 회로는 입력 데이터의 XNUMX/XNUMX 주파수에서 작동하므로 기존 CMOS 복구 회로보다 전력 소모가 적습니다. 시뮬레이션 결과는 이 복구 회로가 단일 XNUMXV 공급 장치로 XNUMXmW 미만의 전력 손실로 작동할 수 있음을 보여줍니다. 모든 시뮬레이션은 HYUNDAI XNUMX µm N-Well CMOS 이중 폴리 이중 금속 기술을 기반으로 합니다.
병렬 시계 및 데이터 복구, CMOS, 광통신, 저전력
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부
Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, "A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 8, pp. 1720-1727, August 2000, doi: .
Abstract: This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_8_1720/_p
부
@ARTICLE{e83-a_8_1720,
author={Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications},
year={2000},
volume={E83-A},
number={8},
pages={1720-1727},
abstract={This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1720
EP - 1727
AU - Hae-Moon SEO
AU - Chang-Gene WOO
AU - Sang-Won OH
AU - Sung-Wook JUNG
AU - Pyung CHOI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2000
AB - This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.
ER -