The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 고속 신호 및 데이터 처리 응용을 위한 통합 고기수 분할 알고리즘을 제안하고 제안된 알고리즘을 기반으로 고기수 병렬 분할기의 설계 및 평가를 제시합니다. 입력 피연산자를 미리 스케일링하고 부분 나머지의 일부 유효 숫자를 중복되지 않은 표현으로 변환함으로써 몫 숫자 선택 테이블을 사용하지 않고 부분 나머지에서 직접 몫 숫자를 얻을 수 있습니다. 성능 평가는 제안된 radix-4 및 radix-8 분할기 아키텍처가 이진 분할기보다 동일한 수준의 하드웨어 복잡성으로 더 빠른 계산을 달성한다는 것을 보여줍니다. 또한 4μm CMOS 기술로 radix-0.35 분배기 칩을 실험적으로 제작하는 방법도 보여줍니다.
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Takafumi AOKI, Kimihiko NAKAZAWA, Tatsuo HIGUCHI, "Design of High-Radix VLSI Dividers without Quotient Selection Tables" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2623-2631, November 2001, doi: .
Abstract: In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2623/_p
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@ARTICLE{e84-a_11_2623,
author={Takafumi AOKI, Kimihiko NAKAZAWA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of High-Radix VLSI Dividers without Quotient Selection Tables},
year={2001},
volume={E84-A},
number={11},
pages={2623-2631},
abstract={In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Design of High-Radix VLSI Dividers without Quotient Selection Tables
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2623
EP - 2631
AU - Takafumi AOKI
AU - Kimihiko NAKAZAWA
AU - Tatsuo HIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.
ER -