The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
부분적으로 병합 가능한 코어를 사용하여 계층적 지적 재산(IP) 보호를 위한 새로운 기술을 제시합니다. 제안된 코어 파티셔닝 기법은 핵심 IP에 대한 100% 보호를 보장하는 동시에 시스템과 병합되는 로직에 대한 테스트 생성을 단순화합니다. Critical-IP는 BIST를 사용해 테스트하기 때문에 코어 내부 회선의 제어성과 관찰성이 향상되고 테스트 적용 시간이 단축된다. ISIT-DLX 및 Picojava 프로세서 코어를 사용한 사례 연구는 우리 기술의 적용 가능성을 보여줍니다.
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Vikram IYENGAR, Hiroshi DATE, Makoto SUGIHARA, Krishnendu CHAKRABARTY, "Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2632-2638, November 2001, doi: .
Abstract: We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2632/_p
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@ARTICLE{e84-a_11_2632,
author={Vikram IYENGAR, Hiroshi DATE, Makoto SUGIHARA, Krishnendu CHAKRABARTY, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores},
year={2001},
volume={E84-A},
number={11},
pages={2632-2638},
abstract={We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2632
EP - 2638
AU - Vikram IYENGAR
AU - Hiroshi DATE
AU - Makoto SUGIHARA
AU - Krishnendu CHAKRABARTY
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
ER -