The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 LUT 기반 FPGA를 위한 CAD 기술 매핑 알고리즘을 제시합니다. FPGA의 상호 연결은 제한된 라우팅 리소스로 수행되어야 하기 때문에 라우팅 가능성은 기술 매핑 알고리즘에서 가장 중요한 목표입니다. 라우팅 가능성을 최적화하기 위해 알고리즘의 목표는 상호 연결을 최소화한 설계를 생성하는 것입니다. Min-cut 알고리즘은 먼저 부울 네트워크를 나타내는 그래프를 클러스터로 분할하여 클러스터 간의 전체 상호 연결 수가 최소가 되도록 사용됩니다. 필요한 상호 연결 수를 더 줄이기 위해 클러스터는 페어링 기술을 통해 더 큰 클러스터로 병합됩니다. 이 알고리즘은 MCNC 벤치마크 회로에서 테스트되었습니다. 다른 LUT 기반 FPGA 매핑 알고리즘과 비교하여 이 알고리즘은 더 나은 라우팅 특성을 제공합니다.
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부
Chi-Chou KAO, Yen-Tai LAI, "A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2690-2696, November 2001, doi: .
Abstract: This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2690/_p
부
@ARTICLE{e84-a_11_2690,
author={Chi-Chou KAO, Yen-Tai LAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs},
year={2001},
volume={E84-A},
number={11},
pages={2690-2696},
abstract={This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2690
EP - 2696
AU - Chi-Chou KAO
AU - Yen-Tai LAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
ER -