The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
VLSI 평면도의 경계 제약 조건은 칩 경계를 따라 배치할 블록 세트를 요구합니다. 따라서 이 블록 세트는 외부 통신을 위해 I/O 패드에 인접할 수 있습니다. 또한 이러한 블록은 내부 라우팅을 방해하지 않도록 중앙 영역에서 멀리 떨어져 있습니다. 본 논문에서는 CBL(Corner Block List) 표현을 사용하여 경계 제약 조건을 갖춘 VLSI 평면도 알고리즘을 고안했습니다. 경계 제약에 대한 CBL 표현의 필요충분조건을 식별합니다. 우리는 조건을 스캔하고 제약 조건 위반을 처벌하기 위한 페널티 함수를 공식화하기 위해 선형 시간 접근 방식을 설계합니다. 평면도를 최적화하기 위해 시뮬레이션된 어닐링 프로세스가 채택되었습니다. MCNC 벤치마크 실험에서는 유망한 결과가 나타났습니다.
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부
Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, "VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2697-2704, November 2001, doi: .
Abstract: Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2697/_p
부
@ARTICLE{e84-a_11_2697,
author={Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation},
year={2001},
volume={E84-A},
number={11},
pages={2697-2704},
abstract={Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2697
EP - 2704
AU - Yuchun MA
AU - Xianlong HONG
AU - Sheqin DONG
AU - Yici CAI
AU - Chung-Kuan CHENG
AU - Jun GU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
ER -