The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 회로의 최대 지연 분포의 정확성을 향상시키기 위해 상관 관계를 고려하는 CMOS 조합 회로의 통계적 정적 타이밍 분석을 위한 새로운 알고리즘을 제시합니다. 알고리즘에서 다루는 상관관계는 논리 게이트에 대한 입력 신호의 도착 시간 분포 간의 상관관계뿐 아니라 논리 게이트의 스위칭 지연 간의 상관관계와 네트의 상호 연결 지연 간의 상관관계도 포함합니다. 우리는 각 지연을 정규 분포로 모델링하고, 두 지연의 최대값을 계산하기 위해 상관 계수와 함께 두 확률론적 변수의 정규 분포를 사용합니다. 알고리즘은 상관관계를 고려하므로 시간복잡도는 다음과 같습니다. O(m2) 최악의 경우에는 m 주어진 회로를 나타내는 그래프의 모서리 수입니다. 그러나 실제 조합 회로의 경우 복잡성은 이보다 적을 것으로 예상됩니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Shuji TSUKIYAMA, Masakazu TANAKA, Masahiro FUKUI, "An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2746-2754, November 2001, doi: .
Abstract: In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2746/_p
부
@ARTICLE{e84-a_11_2746,
author={Shuji TSUKIYAMA, Masakazu TANAKA, Masahiro FUKUI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays},
year={2001},
volume={E84-A},
number={11},
pages={2746-2754},
abstract={In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2746
EP - 2754
AU - Shuji TSUKIYAMA
AU - Masakazu TANAKA
AU - Masahiro FUKUI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.
ER -