The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 메모리 전력 절감을 위한 시스템 수준 접근 방식을 제안합니다. 기본 아이디어는 자주 실행되는 개체 코드를 작은 하위 프로그램 메모리에 할당하고 하위 프로그램 메모리의 공급 전압과 임계 전압을 최적화하는 것입니다. 대규모 메모리에는 전원 공급 장치에서 접지까지의 직접적인 경로가 많이 포함되어 있기 때문에 임계값 이하의 누설 전류로 인한 전력 손실은 동적 전력 손실보다 더 심각합니다. 우리의 접근 방식은 누설 전류로 인한 정적 전력 소모를 포함한 메모리 전력 소모를 최소화하기 위해 하위 프로그램 메모리 크기, 공급 전압 및 임계 전압을 최적화합니다. 또한, 메모리의 전력 소모를 최소화하기 위해 코드 할당, 공급 전압, 문턱 전압을 동시에 결정하는 휴리스틱 알고리즘도 제안된다. 일부 벤치마크 프로그램에 대한 실험에서는 우리의 접근 방식을 사용하지 않는 프로그램 메모리에 비해 최대 80%까지 상당한 에너지 감소를 보여줍니다.
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부
Tohru ISHIHARA, Kunihiro ASADA, "A System Level Optimization Technique for Application Specific Low Power Memories" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2755-2761, November 2001, doi: .
Abstract: A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2755/_p
부
@ARTICLE{e84-a_11_2755,
author={Tohru ISHIHARA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A System Level Optimization Technique for Application Specific Low Power Memories},
year={2001},
volume={E84-A},
number={11},
pages={2755-2761},
abstract={A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - A System Level Optimization Technique for Application Specific Low Power Memories
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2755
EP - 2761
AU - Tohru ISHIHARA
AU - Kunihiro ASADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.
ER -