The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 편지는 효율적인 그래프 기반 진화 최적화 기술과 이를 다중 값 산술 회로의 트랜지스터 수준 설계에 적용하는 방법을 제시합니다. 핵심 아이디어는 다양한 구성 요소의 이종 네트워크를 모델링하기 위해 "색상 터미널이 있는 회로 그래프"를 도입하는 것입니다. 제안된 접근 방식의 잠재력은 4진수 부호 있는 숫자(SD) 전가산기 회로의 실험적 합성을 통해 입증됩니다.
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Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, "Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2808-2810, November 2001, doi: .
Abstract: This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2808/_p
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@ARTICLE{e84-a_11_2808,
author={Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--},
year={2001},
volume={E84-A},
number={11},
pages={2808-2810},
abstract={This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2808
EP - 2810
AU - Masanori NATSUI
AU - Takafumi AOKI
AU - Tatsuo HIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.
ER -