The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
새로운 코드 압축 방법을 갖춘 VLIW(Very Long Instruction Word) 아키텍처가 제안되었습니다. 3D 기하학 프로세서의 경우, 우리는 두 가지 유형의 2-이슈 VLIW 아키텍처인 부동 소수점 실행 가속 VLIW(FP-VLIW)와 데이터 이동 강화 VLIW(MV-VLIW) 아키텍처를 단일 아키텍처의 확장으로 간주합니다. 스트리밍 단일 명령어, 다중 데이터(SS-SIMD) 아키텍처. VLIW 아키텍처에서 흔히 발생하는 코드 팽창 문제를 해결하기 위해 제안된 방법은 소프트웨어 도구를 사용하여 원본 코드를 VLIW 코드로 압축하고 칩의 명령어 스왑 회로로 구성된 간단한 하드웨어 디컴팩터를 통해 VLIW 코드의 압축을 해제하는 것을 가능하게 합니다. 코드 압축을 사용하는 두 VLIW의 속도와 코드 밀도는 동일한 명령어 세트와 동일한 빌딩 블록을 사용하는 SS-SIMD와 비교됩니다. FP-VLIW는 viewperf CDRS-03 벤치마크 프로그램 평가 결과에서 가장 빠른 속도 성능을 보여줍니다. 참고로 사용된 SS-SIMD보다 36% 빠릅니다. 제안된 압축 방법은 SS-SIMD의 95% 코드 밀도를 유지합니다. 한 테스트 프로그램은 MV-VLIW의 코드 밀도가 SS-SIMD의 코드 밀도보다 높다는 것을 보여줍니다. 이 결과는 nops 압축의 장점이 VLIW 페널티보다 클 수 있음을 보여줍니다. 코드 압축을 갖춘 FP-VLIW 아키텍처는 코드 밀도를 크게 저하시키지 않고 1.36배의 속도 성능을 달성합니다.
VLIW, 코드 압축, ASSP, 3D 기하학 프로세서, 컴퓨터 그래픽
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부
Hiroaki SUZUKI, Hiroyuki KAWAI, Hiroshi MAKINO, Yoshio MATSUDA, "Novel VLIW Code Compaction Method for a 3D Geometry Processor" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2885-2893, November 2001, doi: .
Abstract: A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a Single-Streaming Single Instruction, Multiple Data (SS-SIMD) architecture. To solve the code bloat problem which is common to VLIW architectures, the proposed method makes it possible to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the code compaction are compared to the SS-SIMD with the same instruction set and the same building blocks. The FP-VLIW shows the fastest speed performance in the evaluation results of the viewperf CDRS-03 benchmark programs. It is 36% faster than the SS-SIMD used as reference. The proposed compaction method keeps the 95% code density of the SS-SIMD. One test program shows that the code density of the MV-VLIW is higher than that of the SS-SIMD. This result demonstrates that the merit of compacting nops can be greater than the VLIW penalty. The FP-VLIW architecture with the code compaction achieves 1.36 times the speed performance without significant code-density deterioration.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2885/_p
부
@ARTICLE{e84-a_11_2885,
author={Hiroaki SUZUKI, Hiroyuki KAWAI, Hiroshi MAKINO, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Novel VLIW Code Compaction Method for a 3D Geometry Processor},
year={2001},
volume={E84-A},
number={11},
pages={2885-2893},
abstract={A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a Single-Streaming Single Instruction, Multiple Data (SS-SIMD) architecture. To solve the code bloat problem which is common to VLIW architectures, the proposed method makes it possible to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the code compaction are compared to the SS-SIMD with the same instruction set and the same building blocks. The FP-VLIW shows the fastest speed performance in the evaluation results of the viewperf CDRS-03 benchmark programs. It is 36% faster than the SS-SIMD used as reference. The proposed compaction method keeps the 95% code density of the SS-SIMD. One test program shows that the code density of the MV-VLIW is higher than that of the SS-SIMD. This result demonstrates that the merit of compacting nops can be greater than the VLIW penalty. The FP-VLIW architecture with the code compaction achieves 1.36 times the speed performance without significant code-density deterioration.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Novel VLIW Code Compaction Method for a 3D Geometry Processor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2885
EP - 2893
AU - Hiroaki SUZUKI
AU - Hiroyuki KAWAI
AU - Hiroshi MAKINO
AU - Yoshio MATSUDA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a Single-Streaming Single Instruction, Multiple Data (SS-SIMD) architecture. To solve the code bloat problem which is common to VLIW architectures, the proposed method makes it possible to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the code compaction are compared to the SS-SIMD with the same instruction set and the same building blocks. The FP-VLIW shows the fastest speed performance in the evaluation results of the viewperf CDRS-03 benchmark programs. It is 36% faster than the SS-SIMD used as reference. The proposed compaction method keeps the 95% code density of the SS-SIMD. One test program shows that the code density of the MV-VLIW is higher than that of the SS-SIMD. This result demonstrates that the merit of compacting nops can be greater than the VLIW penalty. The FP-VLIW architecture with the code compaction achieves 1.36 times the speed performance without significant code-density deterioration.
ER -