The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 다중 폴딩 증폭기를 갖춘 전류 모드 폴딩 및 보간 아날로그-디지털 변환기(ADC) 아키텍처를 제안합니다. 전류 모드 다중 폴딩 증폭기는 기준 전류원 수를 줄이는 것뿐만 아니라 ADC 내 전력 소모를 줄이기 위해 사용됩니다. 제안된 12비트용 ADC는 0.65 µm n-well CMOS 단일 폴리/이중 금속 공정으로 설계되었습니다. 시뮬레이션 결과는 다음과 같은 차등 비선형성(DNL)을 보여줍니다.
곱셈 접이식 증폭기, ADC, CMOS, 현재 모드, 접기/보간
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Hyung Hoon KIM, Kwang Sub YOON, "A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 2, pp. 563-567, February 2001, doi: .
Abstract: A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_2_563/_p
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@ARTICLE{e84-a_2_563,
author={Hyung Hoon KIM, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers},
year={2001},
volume={E84-A},
number={2},
pages={563-567},
abstract={A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 563
EP - 567
AU - Hyung Hoon KIM
AU - Kwang Sub YOON
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2001
AB - A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
ER -