The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 임베디드 시스템용 멀티스레드 프로세서 아키텍처를 제안하고 다른 임베디드 시스템용 프로세서와 비교 평가한다. 실험 결과는 프로세서 간의 하드웨어 비용과 실행 시간의 균형을 보여줍니다. 제안된 멀티 스레드 프로세서를 임베디드 프로세서로 고려하면 임베디드 시스템의 설계 공간이 확대되고 일부 설계 제약 조건 하에서 더 적합한 아키텍처를 선택할 수 있습니다.
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Shinsuke KOBAYASHI, Yoshinori TAKEUCHI, Akira KITAJIMA, Masaharu IMAI, "Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 748-754, March 2001, doi: .
Abstract: In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_748/_p
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@ARTICLE{e84-a_3_748,
author={Shinsuke KOBAYASHI, Yoshinori TAKEUCHI, Akira KITAJIMA, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation},
year={2001},
volume={E84-A},
number={3},
pages={748-754},
abstract={In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.},
keywords={},
doi={},
ISSN={},
month={March},}
부
TY - JOUR
TI - Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 748
EP - 754
AU - Shinsuke KOBAYASHI
AU - Yoshinori TAKEUCHI
AU - Akira KITAJIMA
AU - Masaharu IMAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.
ER -