The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
준산술 압축 알고리즘을 위한 소프트웨어와 수축기 하드웨어 구현의 조합이 제시됩니다. 하드웨어는 파이프라인 하드웨어 구현으로 구현됩니다. 구현은 알고리즘을 변경하지 않습니다. 그냥 두 부분으로 나누었습니다. 병렬 소프트웨어와 파이프라인 하드웨어의 조합은 압축 효율성의 저하 없이 매우 빠른 압축을 제공할 수 있습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Yair WISEMAN, "A Pipeline Chip for Quasi Arithmetic Coding" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 4, pp. 1034-1041, April 2001, doi: .
Abstract: A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_4_1034/_p
부
@ARTICLE{e84-a_4_1034,
author={Yair WISEMAN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Pipeline Chip for Quasi Arithmetic Coding},
year={2001},
volume={E84-A},
number={4},
pages={1034-1041},
abstract={A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.},
keywords={},
doi={},
ISSN={},
month={April},}
부
TY - JOUR
TI - A Pipeline Chip for Quasi Arithmetic Coding
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1034
EP - 1041
AU - Yair WISEMAN
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2001
AB - A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
ER -