The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 제어 기반 하드웨어를 위한 고급 합성 시스템에서 영역/시간 최적화 알고리즘을 제안합니다. 노드가 응용 프로그램의 제어 흐름에 해당하는 호출 그래프가 주어지면 알고리즘은 영역 및 타이밍 제약 하에서 입력 호출 그래프를 나타내는 상태 전환 그래프 세트를 생성합니다. 알고리즘에서는 첫 번째로 타이밍 제약만을 만족하는 상태전이 그래프를 생성하고, 두 번째로 면적 제약을 만족할 수 있도록 변환한다. 알고리즘은 제어 흐름 그래프에 직접 적용되므로 비트 단위 프로세스 및 조건 분기와 같은 제어 흐름을 처리할 수 있습니다. 또한 이 알고리즘은 응용 프로그램에 대한 단일 호출 그래프에서 둘 이상의 하드웨어 아키텍처 후보를 합성합니다. 애플리케이션 프로그램 설계자는 여러 설계 기준에 따라 후보 중에서 여러 가지 좋은 하드웨어 아키텍처를 선택할 수 있습니다. 여러 제어 기반 하드웨어에 대한 실험 결과는 알고리즘의 효과와 효율성을 보여줍니다.
고급 합성, 제어 기반 하드웨어, 지역/시간 최적화, 일정, 자원 할당
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Nozomu TOGAWA, Masayuki IENAGA, Masao YANAGISAWA, Tatsuo OHTSUKI, "An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 5, pp. 1166-1176, May 2001, doi: .
Abstract: This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_5_1166/_p
부
@ARTICLE{e84-a_5_1166,
author={Nozomu TOGAWA, Masayuki IENAGA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares},
year={2001},
volume={E84-A},
number={5},
pages={1166-1176},
abstract={This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1166
EP - 1176
AU - Nozomu TOGAWA
AU - Masayuki IENAGA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2001
AB - This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.
ER -