The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 하드웨어 곱셈기가 필요 없이 더 높은 신호 속도 및 파이프라인 작업과 함께 계수 스케일링 결과를 저장하기 위해 ROM을 사용하여 곱셈기가 없는 고속 구현을 제안합니다. 일부 매개변수를 변경함으로써 제안된 구조는 하드웨어와 클럭 속도(또는 처리량)의 다양한 조합을 제공합니다. 제안된 구현을 분산 산술(DA) 구현 및 2의 거듭제곱 계수를 사용한 직접 형식 구현과 비교하는 예가 제공됩니다. 결과는 매개변수를 적절하게 선택하면 제안된 구조가 DA 구현과 비교하여 더 적은 하드웨어로 더 빠른 처리 속도를 달성하는 반면 약간 더 많은 하드웨어를 사용하여 직접 형식보다 훨씬 빠르다는 것을 보여줍니다.
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Thanyapat SAKUNKONCHAK, Sawasd TANTARATANA, "A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1479-1487, June 2001, doi: .
Abstract: In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1479/_p
부
@ARTICLE{e84-a_6_1479,
author={Thanyapat SAKUNKONCHAK, Sawasd TANTARATANA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate},
year={2001},
volume={E84-A},
number={6},
pages={1479-1487},
abstract={In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1479
EP - 1487
AU - Thanyapat SAKUNKONCHAK
AU - Sawasd TANTARATANA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.
ER -