The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
정적 CMOS PLA 회로를 위한 새로운 IDDQ 테스트 가능 설계 방법이 제안되었습니다. 이 방법을 사용하여 테스트 가능한 NOR-NOR 유형의 PLA 회로를 설계했습니다. 테스트 가능하게 설계된 PLA 회로의 NOR 평면의 모든 브리징 오류는 4세트의 테스트 입력 벡터를 사용한 IDDQ 테스트를 통해 감지할 수 있음을 보여줍니다. 테스트 입력 벡터는 PLA 회로에서 구현되는 논리 기능과 독립적입니다. PLA 회로는 테스트 시 생성되는 대기 공급 전류가 XNUMX이 되도록 이 방법을 사용하여 설계되었습니다. 따라서 테스트 가능한 설계 방법을 사용하여 PLA 회로에 대한 높은 해상도의 IDDQ 테스트를 얻을 수 있습니다. 이 테스트 가능한 설계 방법을 사용하여 설계된 PLA 회로의 IDDQ 테스트 결과는 예상 출력이 회로에서 생성될 수 있다는 것이 아니라 회로가 NOR 평면에서 브리징 결함 없이 제조된다는 것을 확인합니다. 최첨단 IC 제조에서는 브리징 결함이 자주 발생하기 때문에 테스트 가능한 설계는 신뢰성이 높은 로직 시스템을 구현하는 데 필수적입니다.
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Masaki HASHIZUME, Hiroshi HOSHIKA, Hiroyuki YOTSUYANAGI, Takeomi TAMESADA, "Testable Static CMOS PLA for IDDQ Testing" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1488-1495, June 2001, doi: .
Abstract: A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1488/_p
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@ARTICLE{e84-a_6_1488,
author={Masaki HASHIZUME, Hiroshi HOSHIKA, Hiroyuki YOTSUYANAGI, Takeomi TAMESADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Testable Static CMOS PLA for IDDQ Testing},
year={2001},
volume={E84-A},
number={6},
pages={1488-1495},
abstract={A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Testable Static CMOS PLA for IDDQ Testing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1488
EP - 1495
AU - Masaki HASHIZUME
AU - Hiroshi HOSHIKA
AU - Hiroyuki YOTSUYANAGI
AU - Takeomi TAMESADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.
ER -