The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
CSD(Canonic Signed Digit) 코드로 표현되는 계수를 갖는 저복잡도 선형 위상 FIR 디지털 필터에 대해 2의 거듭제곱 DC 이득을 적용하는 설계 방법이 제안됩니다. 출력 신호 레벨은 입력 신호 레벨로 쉽게 보상될 수 있으므로 많은 단계를 계단식으로 연결해도 고정밀 측정 시스템 등에서 유해한 게인 오류가 발생하지 않습니다. 설계는 크기 응답 제약 조건이 있는 최적화 문제로 공식화되었습니다. CSD 코드에 대해 수정된 정수 선형 계획법은 분기 및 경계 방법으로 해결됩니다. 설계 예에서는 기존 CSD 필터와 비교하여 획득된 필터의 효율성을 보여줍니다. 또한, FPGA(Field Programmable Gate Array)에 필터를 구현하는 영역에 대한 평가 방법을 제안한다. 구현 예에서는 다이 면적을 약간만 늘려도 최소 임계 경로를 얻을 수 있음을 보여줍니다.
FIR 디지털 필터, CSD, 최적화, 정수 프로그래밍, FPGA
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Mitsuru YAMADA, Akinori NISHIHARA, "Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 8, pp. 1997-2003, August 2001, doi: .
Abstract: For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_8_1997/_p
부
@ARTICLE{e84-a_8_1997,
author={Mitsuru YAMADA, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path},
year={2001},
volume={E84-A},
number={8},
pages={1997-2003},
abstract={For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1997
EP - 2003
AU - Mitsuru YAMADA
AU - Akinori NISHIHARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2001
AB - For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.
ER -