The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
딥 서브미크론 기술에는 와이어 및 게이트 지연이 회로 동작에 동일하거나 거의 동일한 영향을 미치는 것으로 간주되는 새로운 설계 기술이 필요합니다. 비동기 속도 독립적(SI) 동작이 게이트 지연 변화에만 견고한 회로는 너무 낙관적일 수 있습니다. 반면에 회로 구축은 완전히 지연에 민감하지 않습니다(DI), 게이트와 와이어 모두에 대해 효과적인 합성 방법이 부족하기 때문에 실용적이지 않습니다. 이 논문은 합성을 위한 새로운 접근 방식을 제시합니다. 세계적으로 DI 그리고 지역적으로 SI 회로. 두 가지 가능한 설계 시나리오에서 작동하는 이 방법은 신호 전환 그래프(Signal Transition Graph)라는 동작 사양에서 시작됩니다(STG) 또는 SI 의 구현 STG 사양. 이 방법은 시스템의 결과적인 동작이 입력 와이어의 지연에 의존하지 않는 방식으로 초기 모델을 국지적으로 수정합니다. 이는 시스템-환경 인터페이스의 지연 둔감성을 보장합니다. 제안된 접근 방식은 일련의 벤치마크에서 성공적으로 테스트되었습니다. 실험 결과에 따르면 DI 인터페이싱은 면적과 속도 측면에서 상대적으로 적당한 비용(면적 패널티 약 40%, 속도 패널티 약 20%)으로 구현되는 것으로 나타났습니다.
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Hiroshi SAITO, Alex KONDRATYEV, Jordi CORTADELLA, Luciano LAVAGNO, Alex YAKOVLEV, Takashi NANYA, "Design of Asynchronous Controllers with Delay Insensitive Interface" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2577-2585, December 2002, doi: .
Abstract: Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2577/_p
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@ARTICLE{e85-a_12_2577,
author={Hiroshi SAITO, Alex KONDRATYEV, Jordi CORTADELLA, Luciano LAVAGNO, Alex YAKOVLEV, Takashi NANYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of Asynchronous Controllers with Delay Insensitive Interface},
year={2002},
volume={E85-A},
number={12},
pages={2577-2585},
abstract={Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Design of Asynchronous Controllers with Delay Insensitive Interface
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2577
EP - 2585
AU - Hiroshi SAITO
AU - Alex KONDRATYEV
AU - Jordi CORTADELLA
AU - Luciano LAVAGNO
AU - Alex YAKOVLEV
AU - Takashi NANYA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).
ER -