The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
클록이 모든 레지스터에 동시에 분배될 필요는 없지만 주기적으로 각 개별 레지스터에 분배된다고 가정하는 회로(반동기 회로)는 일반 동기 회로에 비해 더 높은 주파수 또는 더 작은 클록 트리를 달성할 것으로 예상됩니다. 완전 동기 회로. 본 논문에서는 완전 동기 회로의 클럭 트리를 수정하여 더 높은 주파수의 반동기 회로를 구현하는 회로 설계 방법을 제안한다. 우리는 제안한 방법이 MIPS 연산 코드와 호환되는 4단계 파이프라인 프로세서를 설계함으로써 현재의 실제 설계 환경에 쉽게 통합될 수 있음을 확인합니다. 획득된 프로세서 회로는 이론적 배경을 바탕으로 체계적으로 설계된 최초의 반동기 회로이다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Seiichiro ISHIJIMA, Tetsuaki UTSUMI, Tomohiro OTO, Atsushi TAKAHASHI, "A Semi-Synchronous Circuit Design Method by Clock Tree Modification" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2596-2602, December 2002, doi: .
Abstract: A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2596/_p
부
@ARTICLE{e85-a_12_2596,
author={Seiichiro ISHIJIMA, Tetsuaki UTSUMI, Tomohiro OTO, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Semi-Synchronous Circuit Design Method by Clock Tree Modification},
year={2002},
volume={E85-A},
number={12},
pages={2596-2602},
abstract={A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - A Semi-Synchronous Circuit Design Method by Clock Tree Modification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2596
EP - 2602
AU - Seiichiro ISHIJIMA
AU - Tetsuaki UTSUMI
AU - Tomohiro OTO
AU - Atsushi TAKAHASHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.
ER -