The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 부분 순서 감소를 통해 극적으로 가속화되는 시간 제한 회로용 모듈식 합성 알고리즘을 개발합니다. 이 알고리즘은 계층적 설계의 각 모듈을 개별적으로 합성합니다. 동시에 활성화된 전환의 단일 인터리빙을 고려하여 다른 모듈에 대해 탐색되는 상태 공간을 줄이기 위해 부분 순서 감소를 활용합니다. 이 접근법은 상태 폭발 문제를 더 잘 관리하여 합성 시간을 2배 이상 단축시킵니다. 향상된 합성 시간으로 인해 이전에 가능했던 것보다 더 큰 종류의 시간 제한 회로 합성이 가능해졌습니다.
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부
Tomohiro YONEDA, Eric MERCER, Chris MYERS, "Modular Synthesis of Timed Circuits Using Partial Order Reduction" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2684-2692, December 2002, doi: .
Abstract: This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2684/_p
부
@ARTICLE{e85-a_12_2684,
author={Tomohiro YONEDA, Eric MERCER, Chris MYERS, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modular Synthesis of Timed Circuits Using Partial Order Reduction},
year={2002},
volume={E85-A},
number={12},
pages={2684-2692},
abstract={This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Modular Synthesis of Timed Circuits Using Partial Order Reduction
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2684
EP - 2692
AU - Tomohiro YONEDA
AU - Eric MERCER
AU - Chris MYERS
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
ER -