The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단일 칩 오류로 인해 발생하는 단일 바이트 오류 외에도 위성 메모리 시스템과 같은 일부 응용 프로그램에 사용되는 반도체 메모리는 임의 이중 비트 오류에 매우 취약합니다. 따라서 이중 비트 오류 정정--싱글 설계가 필요합니다. b-비트 바이트 오류 정정(DEC-SbEC) 무작위 이중 비트 오류와 단일 비트 오류를 모두 수정하는 코드 b-비트 바이트 오류. 이 서신은 일반 DEC-S 클래스를 제안합니다.b칩당 8, 16 또는 32비트와 같은 넓은 I/O 데이터를 갖춘 최신 고밀도 DRAM 칩을 사용하는 컴퓨터 메모리 시스템에 적용할 수 있는 EC 코드입니다. 제안된 DEC-S8EC 코드는 8비트 I/O 데이터가 있는 DRAM 칩을 사용하는 메모리 시스템에 적합하며 24비트 및 64비트와 같은 실제 정보 길이를 위해 128개의 검사 비트가 필요합니다.
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Ganesan UMANESAN, Eiji FUJIWARA, "Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 1, pp. 273-276, January 2002, doi: .
Abstract: Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_1_273/_p
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@ARTICLE{e85-a_1_273,
author={Ganesan UMANESAN, Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems},
year={2002},
volume={E85-A},
number={1},
pages={273-276},
abstract={Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.},
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 273
EP - 276
AU - Ganesan UMANESAN
AU - Eiji FUJIWARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2002
AB - Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
ER -