The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 디지털 신호 프로세서의 특정 아키텍처 기능을 활용하여 성능을 향상시키는 새로운 DSP 지향 코드 최적화 방법을 제시합니다. 제안된 방법에서는 루프와 관련된 상위 수준 정보와 배열 액세스의 주소 계산을 유지하면서 소스 코드를 정적 단일 할당 형식으로 변환합니다. 이 정보는 대부분의 디지털 신호 프로세서에서 제공하는 하드웨어 루프 명령어 및 병렬 명령어를 생성하는 데 사용됩니다. 기존의 제어 데이터 흐름 그래프 외에 새로운 그래프를 사용하여 자동 수정 어드레싱 모드를 효율적으로 쉽게 찾을 수 있습니다. 벤치마크 프로그램에 대한 실험 결과, 제안한 방법이 성능 향상에 효과적인 것으로 나타났다.
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부
Jong-Yeol LEE, In-Cheol PARK, "Loop and Address Code Optimization for Digital Signal Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 6, pp. 1408-1415, June 2002, doi: .
Abstract: This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_6_1408/_p
부
@ARTICLE{e85-a_6_1408,
author={Jong-Yeol LEE, In-Cheol PARK, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Loop and Address Code Optimization for Digital Signal Processors},
year={2002},
volume={E85-A},
number={6},
pages={1408-1415},
abstract={This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Loop and Address Code Optimization for Digital Signal Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1408
EP - 1415
AU - Jong-Yeol LEE
AU - In-Cheol PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2002
AB - This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.
ER -