The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
FIR(Finite Impulse Response) 구현의 면적 및 전력 문제를 해결하기 위해 사전 정의된 출력 정확도를 계속 얻을 수 있으면서도 상당한 면적 및 전력 절감을 위해 충실하게 절단된 가산기 기반 FIR 설계가 이 문서에 제시되어 있습니다. 잘린 가산기로 인한 정확도 손실에 대한 해결책으로 FIR에서 잘린 가산기 활용에 대한 정적 오류 분석을 수행하였다. 수학적 분석에 따르면, 주어진 정확도 제약 조건에서 면적 전력 효율적인 FIR 설계를 위한 최적의 절단 가산기 구성을 쉽게 결정할 수 있음을 보여줍니다. 제안된 충실하게 절단된 가산기 설계를 사용하여 다양한 FIR 구현에 대한 평가 결과는 35.4 미만의 전력 소비로 최대 27.9% 및 1%의 면적 및 전력 소비 절감을 달성할 수 있음을 보여줍니다. 울프 균일하게 분포된 무작위 입력에 대한 정확도 손실. 또한 정규 분포 신호에 대한 사례 연구로 심전도(ECG) 신호 필터링을 위해 고정 6탭 FIR이 구현되었으며, 이는 잘린 비트를 최대 10까지 증가시켜도 평균 절대 오차(Ē)는 1보다 작다는 것을 보장할 수 있습니다. 울프 동시에 면적과 전력을 최대 29.7%, 25.3% 절감할 수 있습니다.
Jinghao YE
Waseda University
Masao YANAGISAWA
Waseda University
Youhua SHI
Waseda University
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부
Jinghao YE, Masao YANAGISAWA, Youhua SHI, "Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 9, pp. 1063-1070, September 2020, doi: 10.1587/transfun.2019KEP0010.
Abstract: To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0010/_p
부
@ARTICLE{e103-a_9_1063,
author={Jinghao YE, Masao YANAGISAWA, Youhua SHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy},
year={2020},
volume={E103-A},
number={9},
pages={1063-1070},
abstract={To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.},
keywords={},
doi={10.1587/transfun.2019KEP0010},
ISSN={1745-1337},
month={September},}
부
TY - JOUR
TI - Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1063
EP - 1070
AU - Jinghao YE
AU - Masao YANAGISAWA
AU - Youhua SHI
PY - 2020
DO - 10.1587/transfun.2019KEP0010
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.
ER -