The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 편지에서는 다중 입력 다중 출력(MIMO) 시스템을 위한 낮은 대기 시간, 높은 처리량 및 하드웨어 효율적인 정렬된 MMSE QR 분해(MMSE-SQRD)가 제시됩니다. 복소 행렬을 실제 모델로 확장한 후 실수치 QRD 분해(QRD)를 적용하는 방식과 달리, 복소 영역에서 QRD를 직접 수행하는 좌표 회전 디지털 컴퓨터(CORDIC) 기반의 고도 병렬 분해 방식을 개발하고 그런 다음 복잡한 결과를 실제 결과로 변환합니다. 제안된 방식은 처리 병렬성을 크게 향상시키고 무효화 및 정렬 절차를 단축할 수 있습니다. 게다가, 우리는 4×4 MIMO 검출기에 대한 CORDIC 알고리즘을 사용하여 고도로 병렬인 Gives 회전 구조를 기반으로 하는 MMSE-SQRD의 해당 파이프라인 하드웨어 아키텍처를 설계합니다. 제안된 MMSE-SQRD는 SMIC 55nm CMOS 기술로 구현되어 최대 50M QRD/s 처리량과 단 59킬로게이트(KG)로 218클록 주기의 대기 시간을 달성합니다. 이전 연구와 비교하여 제안된 디자인은 가장 높은 정규화된 처리량 효율성과 가장 낮은 처리 대기 시간을 달성합니다.
Lu SUN
Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS),University of Chinese Academy of Sciences (UCAS)
Bin WU
Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)
Tianchun YE
Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)
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부
Lu SUN, Bin WU, Tianchun YE, "Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 4, pp. 762-767, April 2021, doi: 10.1587/transfun.2020EAL2076.
Abstract: In this letter, a low latency, high throughput and hardware efficient sorted MMSE QR decomposition (MMSE-SQRD) for multiple-input multiple-output (MIMO) systems is presented. In contrast to the method of extending the complex matrix to real model and thereafter applying real-valued QR decomposition (QRD), we develop a highly parallel decomposition scheme based on coordinate rotation digital computer (CORDIC) which performs the QRD in complex domain directly and then converting the complex result to its real counterpart. The proposed scheme can greatly improve the processing parallelism and curtail the nullification and sorting procedures. Besides, we also design the corresponding pipelined hardware architecture of the MMSE-SQRD based on highly parallel Givens rotation structure with CORDIC algorithm for 4×4 MIMO detectors. The proposed MMSE-SQRD is implemented in SMIC 55nm CMOS technology achieving up to 50M QRD/s throughput and a latency of 59 clock cycles with only 218 kilo-gates (KG). Compared to the previous works, the proposed design achieves the highest normalized throughput efficiency and lowest processing latency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020EAL2076/_p
부
@ARTICLE{e104-a_4_762,
author={Lu SUN, Bin WU, Tianchun YE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors},
year={2021},
volume={E104-A},
number={4},
pages={762-767},
abstract={In this letter, a low latency, high throughput and hardware efficient sorted MMSE QR decomposition (MMSE-SQRD) for multiple-input multiple-output (MIMO) systems is presented. In contrast to the method of extending the complex matrix to real model and thereafter applying real-valued QR decomposition (QRD), we develop a highly parallel decomposition scheme based on coordinate rotation digital computer (CORDIC) which performs the QRD in complex domain directly and then converting the complex result to its real counterpart. The proposed scheme can greatly improve the processing parallelism and curtail the nullification and sorting procedures. Besides, we also design the corresponding pipelined hardware architecture of the MMSE-SQRD based on highly parallel Givens rotation structure with CORDIC algorithm for 4×4 MIMO detectors. The proposed MMSE-SQRD is implemented in SMIC 55nm CMOS technology achieving up to 50M QRD/s throughput and a latency of 59 clock cycles with only 218 kilo-gates (KG). Compared to the previous works, the proposed design achieves the highest normalized throughput efficiency and lowest processing latency.},
keywords={},
doi={10.1587/transfun.2020EAL2076},
ISSN={1745-1337},
month={April},}
부
TY - JOUR
TI - Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 762
EP - 767
AU - Lu SUN
AU - Bin WU
AU - Tianchun YE
PY - 2021
DO - 10.1587/transfun.2020EAL2076
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2021
AB - In this letter, a low latency, high throughput and hardware efficient sorted MMSE QR decomposition (MMSE-SQRD) for multiple-input multiple-output (MIMO) systems is presented. In contrast to the method of extending the complex matrix to real model and thereafter applying real-valued QR decomposition (QRD), we develop a highly parallel decomposition scheme based on coordinate rotation digital computer (CORDIC) which performs the QRD in complex domain directly and then converting the complex result to its real counterpart. The proposed scheme can greatly improve the processing parallelism and curtail the nullification and sorting procedures. Besides, we also design the corresponding pipelined hardware architecture of the MMSE-SQRD based on highly parallel Givens rotation structure with CORDIC algorithm for 4×4 MIMO detectors. The proposed MMSE-SQRD is implemented in SMIC 55nm CMOS technology achieving up to 50M QRD/s throughput and a latency of 59 clock cycles with only 218 kilo-gates (KG). Compared to the previous works, the proposed design achieves the highest normalized throughput efficiency and lowest processing latency.
ER -