The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 다양한 공정에서 RO(Ring-Oscillator)를 측정하고 이것이 논리 회로와 SRAM에 미치는 영향을 측정하여 BTI(바이어스 온도 불안정성)의 국지적 변동성을 분석합니다. 7nm FinFET(Fin Field Effect Transistor) 공정, 16/14nm 세대 FinFET 공정, 28nm Planer 공정으로 제작된 TEG(Test Elementary Group)의 RO 측정을 바탕으로 평가한 결과, Negative BTI(NBTI)의 표준편차는 다음과 같습니다. Vth 저하(σ(△V뭐))는 평균값의 제곱근에 비례합니다(μ(△V뭐)) 스트레스를 받을 때마다 Vth 풍미와 다양한 회복 조건. 로컬 BTI 변동량은 게이트 길이, 너비 및 핀 수에 따라 달라지지만 7nm FinFET 프로세스의 로컬 BTI 변동량은 다른 프로세스보다 약간 더 큽니다. 이러한 측정 결과를 바탕으로 측정된 내용을 고려하여 논리 회로에 미치는 영향에 대한 분석 결과를 제시합니다. Vth 7nm FinFET 공정에서 글로벌 NBTI에 대한 의존도. 또한 SRAM 최소 작동 전압에 미치는 영향을 분석합니다(V분)의 민감도 분석을 기반으로 한 SNM(Static Noise Margin)은 무시할 수 없는 수준을 나타냅니다. V분 로컬 NBTI로 인한 성능 저하.
Mitsuhiko IGARASHI
Renesas Electronics Corporation,Kyoto Institute of Technology
Yuuki UCHIDA
Renesas Electronics Corporation
Yoshio TAKAZAWA
Renesas Electronics Corporation
Makoto YABUUCHI
Renesas Electronics Corporation
Yasumasa TSUKAMOTO
Renesas Electronics Corporation
Koji SHIBUTANI
Renesas Electronics Corporation
Kazutoshi KOBAYASHI
Kyoto Institute of Technology
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부
Mitsuhiko IGARASHI, Yuuki UCHIDA, Yoshio TAKAZAWA, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Koji SHIBUTANI, Kazutoshi KOBAYASHI, "An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 11, pp. 1536-1545, November 2021, doi: 10.1587/transfun.2020KEP0017.
Abstract: In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020KEP0017/_p
부
@ARTICLE{e104-a_11_1536,
author={Mitsuhiko IGARASHI, Yuuki UCHIDA, Yoshio TAKAZAWA, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Koji SHIBUTANI, Kazutoshi KOBAYASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM},
year={2021},
volume={E104-A},
number={11},
pages={1536-1545},
abstract={In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.},
keywords={},
doi={10.1587/transfun.2020KEP0017},
ISSN={1745-1337},
month={November},}
부
TY - JOUR
TI - An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1536
EP - 1545
AU - Mitsuhiko IGARASHI
AU - Yuuki UCHIDA
AU - Yoshio TAKAZAWA
AU - Makoto YABUUCHI
AU - Yasumasa TSUKAMOTO
AU - Koji SHIBUTANI
AU - Kazutoshi KOBAYASHI
PY - 2021
DO - 10.1587/transfun.2020KEP0017
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2021
AB - In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.
ER -