The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
상단-K 정렬은 데이터베이스 관리 시스템과 같은 응용 프로그램에서 많이 사용되는 정렬의 변형입니다. 최근에는 정렬 작업을 가속화하기 위해 FPGA(Field Programmable Gate Array)를 사용하는 것이 연구자들의 관심을 끌었습니다. 그러나 기존 하드웨어 상위K 정렬 알고리즘은 리소스 집약적이거나 처리량이 낮습니다. 본 논문에서는 자원 효율적인 최상위K 다음으로 구성된 정렬 아키텍처 L 계단식 분류 단위와 각 분류 단위는 다음과 같이 구성됩니다. P 셀 정렬. K=PL 가변 길이 입력 시퀀스가 처리될 때 가장 큰 요소가 생성됩니다. 이 아키텍처는 더 적은 리소스를 소비하면서 높은 빈도로 작동할 수 있습니다. 실험 결과는 우리의 아키텍처가 이전 연구에 비해 최대 1.2배의 리소스 대 처리량 향상을 달성했음을 보여줍니다.
Binhao HE
Zhejiang University
Meiting XUE
Hangzhou Dianzi Univerisity
Shubiao LIU
Zhejiang University
Feng YU
Zhejiang University
Weijie CHEN
Zhejiang University
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부
Binhao HE, Meiting XUE, Shubiao LIU, Feng YU, Weijie CHEN, "Resource Efficient Top-K Sorter on FPGA" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 9, pp. 1372-1376, September 2022, doi: 10.1587/transfun.2021EAL2103.
Abstract: The top-K sorting is a variant of sorting used heavily in applications such as database management systems. Recently, the use of field programmable gate arrays (FPGAs) to accelerate sorting operation has attracted the interest of researchers. However, existing hardware top-K sorting algorithms are either resource-intensive or of low throughput. In this paper, we present a resource-efficient top-K sorting architecture that is composed of L cascading sorting units, and each sorting unit is composed of P sorting cells. K=PL largest elements are produced when a variable length input sequence is processed. This architecture can operate at a high frequency while consuming fewer resources. The experimental results show that our architecture achieved a maximum 1.2x throughput-to-resource improvement compared to previous studies.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021EAL2103/_p
부
@ARTICLE{e105-a_9_1372,
author={Binhao HE, Meiting XUE, Shubiao LIU, Feng YU, Weijie CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Resource Efficient Top-K Sorter on FPGA},
year={2022},
volume={E105-A},
number={9},
pages={1372-1376},
abstract={The top-K sorting is a variant of sorting used heavily in applications such as database management systems. Recently, the use of field programmable gate arrays (FPGAs) to accelerate sorting operation has attracted the interest of researchers. However, existing hardware top-K sorting algorithms are either resource-intensive or of low throughput. In this paper, we present a resource-efficient top-K sorting architecture that is composed of L cascading sorting units, and each sorting unit is composed of P sorting cells. K=PL largest elements are produced when a variable length input sequence is processed. This architecture can operate at a high frequency while consuming fewer resources. The experimental results show that our architecture achieved a maximum 1.2x throughput-to-resource improvement compared to previous studies.},
keywords={},
doi={10.1587/transfun.2021EAL2103},
ISSN={1745-1337},
month={September},}
부
TY - JOUR
TI - Resource Efficient Top-K Sorter on FPGA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1372
EP - 1376
AU - Binhao HE
AU - Meiting XUE
AU - Shubiao LIU
AU - Feng YU
AU - Weijie CHEN
PY - 2022
DO - 10.1587/transfun.2021EAL2103
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2022
AB - The top-K sorting is a variant of sorting used heavily in applications such as database management systems. Recently, the use of field programmable gate arrays (FPGAs) to accelerate sorting operation has attracted the interest of researchers. However, existing hardware top-K sorting algorithms are either resource-intensive or of low throughput. In this paper, we present a resource-efficient top-K sorting architecture that is composed of L cascading sorting units, and each sorting unit is composed of P sorting cells. K=PL largest elements are produced when a variable length input sequence is processed. This architecture can operate at a high frequency while consuming fewer resources. The experimental results show that our architecture achieved a maximum 1.2x throughput-to-resource improvement compared to previous studies.
ER -