The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
저주파 이퀄라이저와 두 가지 유형의 전송 라인 커플러를 기반으로 하는 전자기 커넥터가 있는 6.5nm CMOS 펄스 트랜시버 칩을 사용하는 65Gb/s 공유 버스가 제시됩니다. 백플레인 배선 양은 1/16배로 줄어들고 전체 커넥터 부피는 1/246배로 줄어듭니다. 위성 프로세서 시스템의 크기와 무게를 60% 줄이고 데이터 속도를 2.6배 높이며 로켓 발사의 강한 충격을 견딜 수 있는 EMC 표준을 충족합니다.
Atsutake KOSUGE
The Univ. of Tokyo
Mototsugu HAMADA
The Univ. of Tokyo
Tadahiro KURODA
The Univ. of Tokyo
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부
Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, "A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 478-486, March 2022, doi: 10.1587/transfun.2021VLP0001.
Abstract: A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0001/_p
부
@ARTICLE{e105-a_3_478,
author={Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System},
year={2022},
volume={E105-A},
number={3},
pages={478-486},
abstract={A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.},
keywords={},
doi={10.1587/transfun.2021VLP0001},
ISSN={1745-1337},
month={March},}
부
TY - JOUR
TI - A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 478
EP - 486
AU - Atsutake KOSUGE
AU - Mototsugu HAMADA
AU - Tadahiro KURODA
PY - 2022
DO - 10.1587/transfun.2021VLP0001
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
ER -