The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 오픈 소스 셀 라이브러리 특성화 프로그램을 제안합니다. 최근에는 무료 오픈소스 실리콘 디자인 커뮤니티가 취미 디자이너, 학원, 업계의 관심을 끌고 있습니다. 이러한 오픈 소스 실리콘 설계는 무료 및 오픈 소스 EDA에서 지원되지만, 우리가 아는 바에 따르면 툴 체인에는 원본 표준 셀을 디지털 회로 설계에 사용하기 위한 셀 라이브러리 특성 분석기가 부족합니다. 본 논문에서는 표준 셀 라이브러리의 타이밍 모델과 전력 모델을 생성할 수 있는 오픈 소스 셀 라이브러리 특성 분석기를 제안합니다.
Shinichi NISHIZAWA
Waseda University
Toru NAKURA
Fukuoka University
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부
Shinichi NISHIZAWA, Toru NAKURA, "Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E106-A, no. 3, pp. 551-559, March 2023, doi: 10.1587/transfun.2022VLP0007.
Abstract: We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2022VLP0007/_p
부
@ARTICLE{e106-a_3_551,
author={Shinichi NISHIZAWA, Toru NAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design},
year={2023},
volume={E106-A},
number={3},
pages={551-559},
abstract={We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.},
keywords={},
doi={10.1587/transfun.2022VLP0007},
ISSN={1745-1337},
month={March},}
부
TY - JOUR
TI - Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 551
EP - 559
AU - Shinichi NISHIZAWA
AU - Toru NAKURA
PY - 2023
DO - 10.1587/transfun.2022VLP0007
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E106-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2023
AB - We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.
ER -