The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단열 논리 회로는 저전력 회로 설계를 위한 가장 매력적인 솔루션 중 하나로 간주됩니다. 본 연구는 많은 점근단열 또는 준단열 논리군 중에서 상대적으로 단순한 구조와 우수한 저전력 성능을 자랑하지만 많은 문제점을 안고 있는 2LAL(Two-level Adiabatic Logic) 회로의 설계를 최적화하는 데 전념하고 있습니다. "역계산"을 위한 타이밍 버퍼. 우리의 초점은 완전히 파이프라인된 2LAL을 위한 "초기 계산 해제" 기술에 있으며, 조기 계산 해제 최적화를 통해 하드웨어 비용을 최소화하기 위한 두 가지 ILP 접근 방식을 제안합니다. 첫 번째 접근 방식에서는 문제가 일종의 스케줄링 문제로 공식화되는 반면, 노드 선택 문제(안정적인 집합 문제)로 다시 공식화됩니다. 제안된 방법의 성능은 ISCAS-85의 여러 벤치마크 회로를 사용하여 평가되었으며, 기존 방법에 비해 최대 70%의 하드웨어 감소가 관찰되었다.
Yuya USHIODA
Japan Advanced Institute of Science and Technology (JAIST)
Mineo KANEKO
Japan Advanced Institute of Science and Technology (JAIST)
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부
Yuya USHIODA, Mineo KANEKO, "ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 3, pp. 600-609, March 2024, doi: 10.1587/transfun.2023VLP0020.
Abstract: Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0020/_p
부
@ARTICLE{e107-a_3_600,
author={Yuya USHIODA, Mineo KANEKO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits},
year={2024},
volume={E107-A},
number={3},
pages={600-609},
abstract={Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.},
keywords={},
doi={10.1587/transfun.2023VLP0020},
ISSN={1745-1337},
month={March},}
부
TY - JOUR
TI - ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 600
EP - 609
AU - Yuya USHIODA
AU - Mineo KANEKO
PY - 2024
DO - 10.1587/transfun.2023VLP0020
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.
ER -